Commit 269c0bfa authored by Markus Holzer's avatar Markus Holzer
Browse files

Merge branch 'qemu' into 'master'

Add CI job for non-x86 vectorization

See merge request pycodegen/pystencils!244
parents 0b740d1f 78c2cbc0
......@@ -124,6 +124,52 @@ ubuntu:
reports:
junit: report.xml
.multiarch_template:
stage: test
except:
variables:
- $ENABLE_NIGHTLY_BUILDS
before_script: &multiarch_before_script
- python3 -c "import pystencils as ps; ps.cpu.cpujit.read_config()"
- sed -i '/^fail_under.*/d' pytest.ini
script:
- export NUM_CORES=$(nproc --all)
- mkdir -p ~/.config/matplotlib
- echo "backend:template" > ~/.config/matplotlib/matplotlibrc
- sed -i 's/--doctest-modules //g' pytest.ini
- env
- pip3 list
- pytest-3 -v -n $NUM_CORES --cov-report html --cov-report term --cov=. --junitxml=report.xml pystencils_tests/test_*vec*.py pystencils_tests/test_random.py
- python3 -m coverage xml
tags:
- docker
artifacts:
when: always
paths:
- coverage_report
reports:
cobertura: coverage.xml
junit: report.xml
arm64:
extends: .multiarch_template
image: i10git.cs.fau.de:5005/pycodegen/pycodegen/arm64
variables:
PYSTENCILS_SIMD: "neon"
QEMU_CPU: "cortex-a72"
before_script:
- *multiarch_before_script
- sed -i s/march=native/march=armv8-a/g ~/.config/pystencils/config.json
ppc64le:
extends: .multiarch_template
image: i10git.cs.fau.de:5005/pycodegen/pycodegen/ppc64le
variables:
PYSTENCILS_SIMD: "vsx"
before_script:
- *multiarch_before_script
- sed -i s/mcpu=native/mcpu=power8/g ~/.config/pystencils/config.json
minimal-conda:
stage: test
except:
......
import math
import os
import platform
from ctypes import CDLL
......@@ -25,6 +26,8 @@ def get_supported_instruction_sets():
global _cache
if _cache is not None:
return _cache.copy()
if 'PYSTENCILS_SIMD' in os.environ:
return os.environ['PYSTENCILS_SIMD'].split(',')
if platform.system() == 'Darwin' and platform.machine() == 'arm64': # not supported by cpuinfo
return ['neon']
elif platform.machine().startswith('ppc64'): # no flags reported by cpuinfo
......
......@@ -32,7 +32,7 @@ inline int32x4_t makeVec_s32(int a, int b, int c, int d)
#endif
inline void cachelineZero(void * p) {
__asm__ volatile("dc zva, %0"::"r"(p));
__asm__ volatile("dc zva, %0"::"r"(p):"memory");
}
inline size_t _cachelineSize() {
......
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