Commit f9ebdb5b authored by Michael Kuron's avatar Michael Kuron Committed by Michael Kuron
Browse files

Update RISC-V vectorization and remove ARM SVE compiler workarounds

parent fddca9ad
Pipeline #41186 passed with stages
in 32 minutes and 20 seconds
......@@ -168,25 +168,19 @@ ppc64le:
- sed -i s/mcpu=native/mcpu=power8/g ~/.config/pystencils/config.json
# Compiler support for SVE is still pretty rough: GCC 10+11 produce incorrect code for fixed-width vectors,
# while Clang 12 produces memory-corrupting heisenbugs unless we enable the address sanitizer.
# In the RNG tests, GCC 10+11 produce an internal compiler error.
# The memory corruption seems to only happen with qemu-user, not with qemu-system.
# Once the compilers and QEMU have improved, this job should be cleaned up to match the others.
# SVE support is still unreliable in GCC 11 (incorrect code for fixed-width vectors, internal compiler errors).
extends: .multiarch_template
PYSTENCILS_SIMD: "sve256,sve512,sve"
ASAN_OPTIONS: detect_leaks=0
LD_PRELOAD: /usr/lib/aarch64-linux-gnu/
- *multiarch_before_script
- sed -i s/march=native/march=armv8-a+sve/g ~/.config/pystencils/config.json
- sed -i s/g\+\+/clang++/g ~/.config/pystencils/config.json
# The RISC-V vector extension is still experimental and needs special compiler flags.
# Once they are officially released, this job should be cleaned up to match the others.
# RISC-V vector extension are currently not supported by GCC.
# Also, the image is built without the libomp package which is not yet available on Ubuntu.
extends: .multiarch_template
......@@ -194,7 +188,7 @@ riscv64:
QEMU_CPU: "rv64,v=true"
- *multiarch_before_script
- sed -i 's/march=native/march=rv64imfdv0p10 -menable-experimental-extensions/g' ~/.config/pystencils/config.json
- sed -i 's/march=native/march=rv64imfdv/g' ~/.config/pystencils/config.json
- sed -i s/g\+\+/clang++/g ~/.config/pystencils/config.json
- sed -i 's/fopenmp/fopenmp=libgomp -I\/usr\/include\/riscv64-linux-gnu/g' ~/.config/pystencils/config.json
......@@ -50,8 +50,8 @@ def get_vector_instruction_set_riscv(data_type='double', instruction_set='rvv'):
'|': 'mor_mm[0, 1]',
'blendv': 'merge_vvm[2, 0, 1]',
'any': 'popc_m[0]',
'all': 'popc_m[0]',
'any': 'cpop_m[0]',
'all': 'cpop_m[0]',
result = dict()
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