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Commit 815edd12 authored by Jan Hoenig's avatar Jan Hoenig
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Fixed imports

parent db24a475
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......@@ -7,6 +7,15 @@ from sympy import S
from pystencils.llvm.control_flow import Loop
def generateLLVM(ast_node):
"""
Prints the ast as llvm code
"""
module = ir.Module()
builder = ir.IRBuilder()
printer = LLVMPrinter(module, builder)
return printer._print(ast_node)
class LLVMPrinter(Printer):
"""Convert expressions to LLVM IR"""
......@@ -133,10 +142,3 @@ class LLVMPrinter(Printer):
def emptyPrinter(self, expr):
raise TypeError("Unsupported type for LLVM JIT conversion: %s"
% type(expr))
def generateLLVM(astNode):
module = ir.Module()
builder = ir.IRBuilder()
printer = LLVMPrinter(module, builder)
return printer._print(astNode)
from pystencils.cpu.kernelcreation import createKernel
from pystencils.backends.llvm import generateLLVM
\ No newline at end of file
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