ARM has a cache line zero instruction that prevents data that will be... (366e3de2) · Commits · pycodegen / pystencils

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Commit 366e3de2 authored 4 years ago by

Michael Kuron Committed by Michael Kuron 4 years ago

ARM has a cache line zero instruction that prevents data that will be...

ARM has a cache line zero instruction that prevents data that will be overwritten anyway from being loaded from RAM. Kind of a non-temporal store light.

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This commit is part of merge request !225. Comments created here will be created in the context of that merge request.

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ARM has a cache line zero instruction that prevents data that will be...