I was looking at how to vectorize the Philox RNG yesterday. Before I knew it, I had implemented a working RNG using AES-NI instructions
There is one place that could be optimized because I fall back to scalar instructions: I failed to reimplement
_mm_cvtepu64_pd (the solution from https://stackoverflow.com/a/41148578 produces incorrect results in the least-significant half of the mantissa). Perhaps someone else can try to fix that.
I did not integrate this with the
vector_instruction_set parameter of the code generation. Perhaps you can do that, @bauer. It needs support for SSE2 and AES instructions (which look like SSE2 instructions, but their availability is determined by a separate CPUID flag). It will also make use of
_mm_cvtepu64_pd from AVX512 if available (these are 128-bit instructions that actually look like SSE2 instructions).