Remove support for non-power-of-2 SVE vector widths

ARM retroactiveley removed non-power-of-2 vector widths from SVE last year. This allows us to remove some code. While we're at it, also enable CI testing for 128-bit width (which is what the ARM Neoverse N2 and V1 have).

pystencils in principle also supports 1024 and 2048 bits, which are the other two sizes that the SVE spec allows (for a total of five sizes, not 15 like before the non-power-of-2 sizes were removed), but Linux does not really support them. Both qemu-user and the Linux kernel will cap the width at 512 bits for this reason. Setting it to something higher at runtime will break any user-space executables that is not aware -- in our case the Docker container will just hang on startup. For details, see https://github.com/torvalds/linux/commit/4ffa09a939ab6d95655b3aee6ff79de48df95be7, https://github.com/torvalds/linux/blob/v6.2/Documentation/arm64/sve.rst#9--system-runtime-configuration and https://blog.linuxplumbersconf.org/2017/ocw/system/presentations/4671/original/plumbers-dm-2017.pdf. There is no hardware available (or even announced) that will have more than 512 bits, so it doesn't actually matter right now. There will probably one day be Linux distributions available that have more than 512 bits supported by their entire userspace (at which point these widths should be added to the CI job) -- glibc 2.34 is a requirement, but we already have that in our Docker image.

pystencils/backends/arm_instruction_sets.py

@@ -151,9 +151,7 @@ def get_vector_instruction_set_arm(data_type='double', instruction_set='neon'):
         result['any'] = f'vaddlvq_u8(vreinterpretq_u8_u{bits[data_type]}({{0}})) > 0'
         result['all'] = f'vaddlvq_u8(vreinterpretq_u8_u{bits[data_type]}({{0}})) == 16*0xff'
 
-    if instruction_set == 'sve' or bitwidth & (bitwidth - 1) == 0:
-        # only power-of-2 vector sizes will evenly divide a cacheline
-        result['cachelineSize'] = 'cachelineSize()'
-        result['cachelineZero'] = 'cachelineZero((void*) {0})'
+    result['cachelineSize'] = 'cachelineSize()'
+    result['cachelineZero'] = 'cachelineZero((void*) {0})'
 
     return result