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RISC-V cacheline zero

Michael Kuron requested to merge rvv into master

The instruction was added to RISC-V in early 2022 as part of the "Zicboz" extension ( I assume it's going to be available on any forthcoming RISC-V HPC processor (e.g. the Ventana Veyron V1). It is supported by Clang 15+ and GCC 11+.

However, we still need to wait for the QEMU 8 release ( before we can test it in CI. The multiarch Docker images ( sometimes take a few months after the corresponding QEMU release. If they go straight to QEMU 8.1, we can also switch on SIMD autodetection (


Edited by Michael Kuron

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