RISC-V cacheline zero (!326) · Merge requests · pycodegen / pystencils · GitLab

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Michael Kuron requested to merge rvv into master Apr 16, 2023

The cbo.zero instruction was added to RISC-V in early 2022 as part of the "Zicboz" extension (https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf). I assume it's going to be available on any forthcoming RISC-V HPC processor (e.g. the Ventana Veyron V1). It is supported by Clang 15+ and GCC 11+.

However, we still need to wait for the QEMU 8 release (https://github.com/qemu/qemu/commit/a939c500793ae7672defe5e3dc83220576a7b202) before we can test it in CI. The multiarch Docker images (https://github.com/multiarch/qemu-user-static) sometimes take a few months after the corresponding QEMU release. If they go straight to QEMU 8.1, we can also switch on SIMD autodetection (https://github.com/qemu/qemu/commit/4333f0924c2f2ca8efaebaed8c24f55f77d8b013).

Requires https://i10git.cs.fau.de/pycodegen/pycodegen/-/merge_requests/16

Edited Apr 22, 2024 by Michael Kuron