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Vectorization improvements

Merged Vectorization improvements
ppc into master
All threads resolved!
Merged Michael Kuron requested to merge ppc into master
All threads resolved!

After we cleaned up vectorization support as part of our ARM Neon experiments a few weeks ago (!188 (merged), !220 (merged), !222 (merged)), I did the same thing with AltiVec/VSX intrinsics for POWER processors. Adding a new SIMD instruction set to pystencils really is just a matter of some quick find-and-replace now. I had test access to a POWER8 machine today, ran in both little-endian and big-endian mode, and all tests passed. So pystencils now actually supports all SIMD instruction sets out there (ignoring MIPS and SPARC processors, which are essentially dead).

This pull request also contains some minor unrelated changes:

  • switches the AES RNG to aligned stores
  • adds a missing pytest.importorskip
  • fixes the vec_any/vec_all operations (which used to only work on 256 bit doubles)
  • removes the q_registers argument from get_vector_instruction_set because there is no point in using half-width vectors
  • fix the AES-NI RNG on Ice Lake/Tiger Lake processors
Edited by Michael Kuron

Merge request reports

Pipeline #31223 passed

Stage:

    Pipeline passed for bdaeaa95 on ppc

    Test coverage 89.01% (-0.45%) from 1 job
    Approval is optional

    Merged by Markus HolzerMarkus Holzer 3 years ago (Mar 29, 2021 8:31pm UTC)

    Merge details

    • Changes merged into master with b075b723 (commits were squashed).
    • Deleted the source branch.

    Pipeline #31225 passed

    Stage:
      Stage:

        Pipeline passed for b075b723 on master

        Test coverage 89.01% (-0.45%) from 1 job

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