After we cleaned up vectorization support as part of our ARM Neon experiments a few weeks ago (!188 (merged), !220 (merged), !222 (merged)), I did the same thing with AltiVec/VSX intrinsics for POWER processors. Adding a new SIMD instruction set to pystencils really is just a matter of some quick find-and-replace now. I had test access to a POWER8 machine today, ran in both little-endian and big-endian mode, and all tests passed. So pystencils now actually supports all SIMD instruction sets out there (ignoring MIPS and SPARC processors, which are essentially dead).
This pull request also contains some minor unrelated changes:
- switches the AES RNG to aligned stores
- adds a missing
pytest.importorskip - fixes the
vec_any/vec_alloperations (which used to only work on 256 bit doubles) - removes the
q_registersargument fromget_vector_instruction_setbecause there is no point in using half-width vectors - fix the AES-NI RNG on Ice Lake/Tiger Lake processors