Skip to content
GitLab
Projects Groups Snippets
  • /
  • Help
    • Help
    • Support
    • Community forum
    • Submit feedback
    • Contribute to GitLab
  • Sign in
  • pystencils pystencils
  • Project information
    • Project information
    • Activity
    • Labels
    • Members
  • Repository
    • Repository
    • Files
    • Commits
    • Branches
    • Tags
    • Contributors
    • Graph
    • Compare
  • Issues 18
    • Issues 18
    • List
    • Boards
    • Service Desk
    • Milestones
  • Merge requests 6
    • Merge requests 6
  • CI/CD
    • CI/CD
    • Pipelines
    • Jobs
    • Schedules
  • Deployments
    • Deployments
    • Environments
    • Releases
  • Monitor
    • Monitor
    • Incidents
  • Analytics
    • Analytics
    • Value stream
    • CI/CD
    • Repository
  • Wiki
    • Wiki
  • Snippets
    • Snippets
  • Activity
  • Graph
  • Create a new issue
  • Jobs
  • Commits
  • Issue Boards
Collapse sidebar
  • pycodegen
  • pystencilspystencils
  • Merge requests
  • !228

Vectorization improvements

  • Review changes

  • Download
  • Email patches
  • Plain diff
Merged Michael Kuron requested to merge ppc into master Mar 16, 2021
  • Overview 5
  • Commits 9
  • Pipelines 20
  • Changes 15

After we cleaned up vectorization support as part of our ARM Neon experiments a few weeks ago (!188 (merged), !220 (merged), !222 (merged)), I did the same thing with AltiVec/VSX intrinsics for POWER processors. Adding a new SIMD instruction set to pystencils really is just a matter of some quick find-and-replace now. I had test access to a POWER8 machine today, ran in both little-endian and big-endian mode, and all tests passed. So pystencils now actually supports all SIMD instruction sets out there (ignoring MIPS and SPARC processors, which are essentially dead).

This pull request also contains some minor unrelated changes:

  • switches the AES RNG to aligned stores
  • adds a missing pytest.importorskip
  • fixes the vec_any/vec_all operations (which used to only work on 256 bit doubles)
  • removes the q_registers argument from get_vector_instruction_set because there is no point in using half-width vectors
  • fix the AES-NI RNG on Ice Lake/Tiger Lake processors
Edited Mar 21, 2021 by Michael Kuron
Assignee
Assign to
Reviewers
Request review from
Time tracking
Source branch: ppc